SHENZHEN, China – Huawei is bringing a new chip architecture into its smartphone business, advancing an effort to supply the processors it needs despite U.S.-led restrictions on access to advanced semiconductor technology. Its approach could help China extract more computing power from the manufacturing processes available to it.

The strategy is moving from research presentations toward products. On September 7, Huawei introduced its Mate XT2 foldable phones with a Kirin 9050 Pro processor using the company’s LogicFolding architecture, according to Reuters’ launch report. Sales are scheduled to begin on September 12.

The development matters because chip performance increasingly depends on how efficiently components exchange information. Huawei is seeking gains through tighter integration, potentially reducing some of the disadvantages imposed by restricted access to leading fabrication technology. Its published results provide grounds for taking that effort seriously. They do not yet establish a broad manufacturing advantage over foreign competitors.

A Different Route to More Powerful Chips

He Tingbo, the head of Huawei’s semiconductor business, presented the approach at the IEEE International Symposium on Circuits and Systems in Shanghai in May. The official conference program described her address as an examination of how semiconductor performance could advance when further transistor shrinking becomes difficult.

Huawei calls its framework the Tau Scaling Law, using the Greek letter for a characteristic time delay. LogicFolding is one implementation: circuits are divided among vertically stacked active layers, bringing connected elements closer together. Shorter wires can reduce electrical resistance and capacitance, helping signals arrive sooner and lowering the energy needed to move them. The method is set out in He’s July research paper.

In a September technical paper, He reported roughly 55 percent greater transistor density for Kirin 2026 and a 41 percent reduction in power consumption for its CPU performance core in a specified comparison with Kirin 9030 Pro at equivalent performance. Those are Huawei’s measurements under particular test conditions, rather than a finding that every application or the entire phone will consume 41 percent less power.

For Huawei and its manufacturing partners, the practical attraction is substantial. Better use of existing fabrication capabilities could help sustain improvements in phones and, eventually, artificial intelligence systems without requiring every gain to come from a smaller transistor.

What the 1.4 Nanometer Target Means

Huawei’s most attention-grabbing ambition is a transistor density equivalent to a 1.4-nanometer process by 2031. That was a future target when announced, and Huawei supplied no independent performance data at the event, Reuters reported in May.

Stacking can increase the number of transistors above a given footprint while leaving their individual dimensions unchanged. Equivalent density therefore does not establish equivalent performance, energy use or manufacturing cost. It also does not mean Huawei has developed a conventional 1.4-nanometer fabrication process.

Competitors are pursuing integration alongside advances in fabrication. TSMC has announced plans to begin A14 production in 2028, while also expanding technologies for stacking chips and connecting processors with memory. Its technology roadmap illustrates why Huawei’s progress must be judged against a moving international benchmark.

The Manufacturing Test

The underlying idea of three-dimensional integration is well established. Belgium’s Imec documented hybrid bonding with a two-micrometer contact pitch in a die-to-wafer demonstration in 2024, alongside wafer-to-wafer research reaching 0.4 micrometers. These are different processes and development stages; they show that fine vertical connections were already an active field of research. Imec’s technical announcement also describes the demanding surface preparation and alignment involved.

Huawei says its Kirin 2026 implementation achieves a 1.5-micrometer bonding pitch. The challenge is to make those connections reliably while controlling heat inside a compact device. He’s September paper describes selective placement of active circuits to prevent hot spots and acknowledges that running the design for maximum performance can increase power density. Huawei’s account makes clear that efficiency depends on engineering choices and operating conditions.

Avoiding extreme-ultraviolet, or EUV, lithography, the technology restricted from sale to China, would not by itself eliminate dependence on Western equipment. The Dutch equipment maker ASML also supplies deep-ultraviolet, or DUV, systems and reported stronger-than-expected Chinese demand for that business in its 2025 annual report. A different architecture does not replace the entire manufacturing supply chain.

The Stakes for China

Huawei’s longer-term plan extends LogicFolding to Ascend AI accelerators around 2030, according to its published technical roadmap. The intended expansion matters because the ability to supply useful computing capacity depends on more than an individual chip: memory, interconnections and software must work efficiently together.

If the approach delivers competitive performance at sustainable cost, it could give Chinese customers more viable domestic options and reduce the leverage associated with some technology restrictions. That outcome remains conditional. Product-level comparisons, production yields and sustained delivery volumes will determine how far the advantage extends.

For Huawei, the immediate opportunity is to turn its reported engineering gains into processors that customers can buy and use reliably. Success on that measure would constitute an important industrial advance, even before the company reaches its most ambitious density targets.